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width=8 poly=0x2f init=0x43 refin=false refout=false xorout=0x00 check=0x0c residue=0x00 name=(none)
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// CRC
crc=0x43; //
for(j=0;j<9;j++)
{
crc ^= tmp[j];
for(i=0;i<8;i++)
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}
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WriteSI4432(0x06, 0x05); // interrupt all disable
WriteSI4432(0x07, 0x01); // to ready mode
WriteSI4432(0x09, 0x7f); // cap = 12.5pf
WriteSI4432(0x0A, 0x06); // uC CLK: 1 MHz
WriteSI4432(0x73, 0x00); // no frequency offset
WriteSI4432(0x74, 0x00); // no frequency offset
WriteSI4432(0x75, 0x53); // 430-440MHz range
WriteSI4432(0x76, 0x62); // 0x621A-433.924
WriteSI4432(0x77, 0x1A); //
WriteSI4432(0x79, 0x00); // no frequency hopping
WriteSI4432(0x7a, 0x00); // no frequency hopping
// 9090/2
WriteSI4432(0x1C, 0x81); // 01 IF Filter Bandwidth
WriteSI4432(0x1D, 0x44); // 44 AFC Loop Gearshift Override
WriteSI4432(0x1E, 0x0A); // 0A AFC Timing Control
WriteSI4432(0x1F, 0x05); // 00 Clock Recovery Gearshift Override
WriteSI4432(0x20, 0x28); // 64 Clock Recovery Oversampling Ratio
WriteSI4432(0x21, 0xA0); // 01 Clock Recovery Offset 2
WriteSI4432(0x22, 0x18); // 47 Clock Recovery Offset 1
WriteSI4432(0x23, 0xD2); // AE Clock Recovery Offset 0
WriteSI4432(0x24, 0x08); // 12 Clock Recovery Timing Loop Gain 1
WriteSI4432(0x25, 0x19); // 8F Clock Recovery Timing Loop Gain 0
WriteSI4432(0x2A, 0x00); // 00 AFC Limiter
WriteSI4432(0x69, 0x60); // 60 AGC Override 1
WriteSI4432(0x70, 0x26); // Manchester,
WriteSI4432(0x71, 0x22); // FSK, FIFO
WriteSI4432(0x72, 31); // 31*625=19375 ( )
WriteSI4432(0x34,10); // 10 - 4-
WriteSI4432(0x35,0x1A); // preambula threshold
WriteSI4432(0x36,0x15); // 3 0x15
WriteSI4432(0x37,0xB9); // 2 0xB9
WriteSI4432(0x27,0x2C); // RSSI
//
WriteSI4432(0x33, 0x0A); // fixpklen=1, Synchronization Word 3 and 2
WriteSI4432(0x32, 0x00); //
WriteSI4432(0x30, 0x80); // Skip2ph, Enable Packet RX Handling=0 ( Skip2ph...)
WriteSI4432(0x3E, 0x08); // 8
WriteSI4432(0x0B, 0x12); // GPIO0 TX
WriteSI4432(0x0C, 0x15); // GPIO1 RX
// FIFO TX
WriteSI4432(0x08, 0x01);// 0x01 Operating Function Control 2
WriteSI4432(0x08, 0x00);// 0x00 Operating Function Control 2
// FIFO RX
WriteSI4432(0x08, 0x02);// 0x02 Operating Function Control 2
WriteSI4432(0x08, 0x00);// 0x00 Operating Function Control 2
// : , ,
WriteSI4432(0x05, 0x02); //
WriteSI4432(0x06, 0x00);
// , NIRQ . 1
SI4432_stat[0] = ReadSI4432(0x03);
SI4432_stat[1] = ReadSI4432(0x04);
WriteSI4432(0x07, 0x05); //
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if (si_int) // SI4432
{
//
SI4432_stat[0] = ReadSI4432(0x03);
SI4432_stat[1] = ReadSI4432(0x04);
SI4432_RSSI = ReadSI4432(0x26);
if (SI4432_stat[0]&0x02)
{
WriteSI4432(0x07, 0x01); // . . ,
SI4432_ReadFIFO(); // FIFO 8
TPMS_Parsing(); // CRC
// FIFO
WriteSI4432(0x08, 0x02); // 0x02 Operating Function Control 2
WriteSI4432(0x08, 0x00); // 0x00 Operating Function Control 2
//WriteSI4432(0x07, 0x05); //
}
else
{
// FIFO TX
WriteSI4432(0x08, 0x01);// 0x01 Operating Function Control 2
WriteSI4432(0x08, 0x00);// 0x00 Operating Function Control 2
// FIFO RX
WriteSI4432(0x08, 0x02);// 0x02 Operating Function Control 2
WriteSI4432(0x08, 0x00);// 0x00 Operating Function Control 2
}
if (SI4432_stat[0]&0x80)
{
// FIFO RX
WriteSI4432(0x08, 0x02);// 0x02 Operating Function Control 2
WriteSI4432(0x08, 0x00);// 0x00 Operating Function Control 2
}
WriteSI4432(0x07, 0x05); //
si_int=0;
}
SI4432_ReadFIFOïŒïŒé¢æ°ã¯ãã»ã³ãµãŒããã®ããŒã¿ãå«ãã¬ã·ãŒããŒãããã¡ãŒãã8ãã€ããèªã¿åãã ãã§ãã
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ãªã³ã¯
- ãã¹ããŒãããããŒãã£ãªããžããã¯ã·ã ã«ã
- github.com/jopohl/urh
- habr.com/ru/company/neuronspace/blog/434634
- www.rapidtables.com/convert/number/hex-to-binary.html
- www.rapidtables.com/convert/number/binary-to-hex.html
- eleif.net/manchester.html
- hackaday.com/2019/06/27/reverse-engineering-cyclic-redundancy-codes
- ç§ã®ãŠãŒãã£ãªãã£ããµã³ãã«ããã±ãŒãžãCRCã®éžæãã¢ãŒã«ã€ããã¹ã¯ãŒã "tPmSutiLity" dropmefiles.com/MtS9W "
- i56578-swl.blogspot.com/2017/08/eavesdropping-wheels-close-look-at-tpms.html
- www.rtl-sdr.com/tag/tpms