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ããã§ãå®æããã¢ãã«ãã©ãã§å ¥æã§ããŸããïŒç§ãã¡ãéçºããŠããã¢ãã©ã€ã¶ãŒãšãŸã£ããåãåé¡ã解決ãããããžã§ã¯ãããããŸãããããã€ãã®æ©èœããããŸããæåã®æ©èœã¯ãã¶ã€ãªã³ã¯ã¹FPGAçšã§ãã第äºã«ãããã¯å®å šã«ææžåãããŠããŸããããªããšãåäœããŸããæ¢è£œã®ãã¬ããããŒããè³Œå ¥ããŠãæ¢è£œã®ãã€ããªã³ãŒãã§åããããšãã§ããŸã...ãããŠããã€ãã®æ©èœãååŸããŸããã©ããªç ç²ãæã£ãŠãããã€ã¹ãå¿ èŠãšãã人ã¯èª°ã§ãããã®éããã©ãããšãã§ããŸãããããã誰ããããéçºããæ¹æ³ãç¥ããŸããããã®ãããžã§ã¯ãã¯ããã«ãããŸãã\ ulpi_wrapper \ testbenchãã£ã¬ã¯ããªå ULPIã®ã©ãããŒãµãã·ã¹ãã ããã¹ãããããã®äžé£ã®ãã¡ã€ã«ããããŸãã圌ãã¯IcarusVerilogç°å¢ã§ã®ã¢ããªã³ã°ãæšå¥šããŠããŸãããç§ã¯ããã€ããŠããŸããããSystemCèšèªã§ãããè¡ãæ¹æ³ã®è¡šé¢ã«æå³ã®ãã説æã¯èŠã€ãããŸããã§ããããã®ãããModelSimç°å¢ã§äœæ¥ãç¶ããããšã«ããŸããããããã©ã®ããã«çµããããç¥ã£ãŠããã...ããããç§ã¯ç¥ããŸããã§ãããããã§ãç 究ãå§ããŸããããã¬ãŒã³ããŒã·ã§ã³ã®éçšã§ãæåãšå€±æã®äž¡æ¹ã瀺ãããŸãã倱æããå§ããŸããããããããã°ã誰ãã倱æããªãæ¹æ³ãç解ã§ããŸãã
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transcript on
if ![file isdirectory verilog_libs] {
file mkdir verilog_libs
}
if ![file isdirectory vhdl_libs] {
file mkdir vhdl_libs
}
vlib verilog_libs/altera_ver
vmap altera_ver ./verilog_libs/altera_ver
vlog -vlog01compat -work altera_ver {c:/intelfpga_lite/17.1/quartus/eda/sim_lib/altera_primitives.v}
vlib verilog_libs/lpm_ver
vmap lpm_ver ./verilog_libs/lpm_ver
vlog -vlog01compat -work lpm_ver {c:/intelfpga_lite/17.1/quartus/eda/sim_lib/220model.v}
vlib verilog_libs/sgate_ver
vmap sgate_ver ./verilog_libs/sgate_ver
vlog -vlog01compat -work sgate_ver {c:/intelfpga_lite/17.1/quartus/eda/sim_lib/sgate.v}
ããããæåŸã«-æããã«å¿ èŠãªãã®ã®ã¢ã»ã³ããªãç§ã¯ãããulpi_wrapper.vãã¡ã€ã«ã®ååã§å€æããŸãïŒ
vlog -vlog01compat -work work +incdir+C:/Work/UsbHead1/SystemCPlay {C:/Work/UsbHead1/SystemCPlay/ulpi_wrapper.v}
vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -L UsbHead1 -voptargs="+acc" lalala
add wave *
view structure
view signals
run 10 us
æ¬åœã«ã Verilogã¢ãžã¥ãŒã«ã®ã¢ã»ã³ããªããããSystemCã§ã®ã¢ãžã¥ãŒã«ã®ã¢ã»ã³ããªã®ãã³ãã¯ãããŸãããå¯äžã®æ®å¿µãªç¹ã¯ããã®DOãã¡ã€ã«ã¯ã·ãã¥ã¬ãŒã·ã§ã³ãéå§ãããã³ã«èªåçã«äœæãããããããããååŸããŠç·šéããããšã¯ã§ããŸãããéåžžã«è€éãªTCLã¹ã¯ãªããã«ãã£ãŠäœæãããŸãããããæ¯é ãã欲æ±ã¯ãããŸãããããããéœæ°ãªååæã«ã€ããŠã®èšäºã®åŸããã®ãããªããããªããšã¯ãããããçç±ã§ã¯ãªãããšã¯ããããæããã§ãã確ãã«ããã¹ãŠããã§ã«ããã«ãããŸããå¯äžã®æ®å¿µãªç¹ã¯ãããã¥ã¡ã³ãã«ãã¹ã¯ãªããããã®æ¹æ³ã§äœæããããšãããããå®è¡ããããšãã§ããããšèšèŒãããŠãããäŸã«ãã³ãããªãããšã§ããããŠãå®éšçã«ãã¹ãŠãæšæž¬ããŸãããããã¡ã€ã«CïŒ\ Work \ UsbHead1 \ SystemCPlay \ myrun.doãäœæããããã«å¶åŸ¡ã移ããŠã¿ãŸãããŸãã次ã®ããã«ããããšããŸãã
ã¡ã€ã³ã®DOãã¡ã€ã«ã¯åŒãç¶ãçæãããŸããããã®æ«å°Ÿã¯æ¬¡ã®ããã«ãªããŸãã
vlog -sv -work UsbHead1 +incdir+C:/Work/UsbHead1/UsbHead1/synthesis/submodules {C:/Work/UsbHead1/UsbHead1/synthesis/submodules/UsbHead1_master_0_b2p_adapter.sv}
vlog -sv -work UsbHead1 +incdir+C:/Work/UsbHead1/UsbHead1/synthesis/submodules {C:/Work/UsbHead1/UsbHead1/synthesis/submodules/UsbHead1_master_0_timing_adt.sv}
vlog -vlog01compat -work work +incdir+C:/Work/UsbHead1/SystemCPlay {C:/Work/UsbHead1/SystemCPlay/ulpi_wrapper.v}
vsim -t 1ps -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver -L rtl_work -L work -L UsbHead1 -voptargs="+acc" lalala
do C:/Work/UsbHead1/SystemCPlay/myrun.do
Verilogãã¡ã€ã«ããŸã ã³ã³ãã€ã«ãããŠããããšãããããŸãããã®åŸãã¢ããªã³ã°ããã»ã¹ãéå§ãããŸãïŒãã¹ãã®å®è¡äžã«ããã衚瀺ãããŸããããvsimã³ãã³ãããã®ããã»ã¹ãéå§ããŠããããšã¯ç¢ºãã§ãïŒããã®åŸãå¶åŸ¡ãèæ¬ããã®ã¹ã¯ãªããã¯ã衚瀺ããã»ã¹ãå¶åŸ¡ããå¿ èŠããããŸããããããããã§ãã¢ã»ã³ããªã管çããããšã¯ã§ããŸãããåéããããã¡ã€ã«ãååã§ãªãå Žåãç§ãã¡ãäœããããããšãèš±å¯ãããåã«ãã·ã¹ãã ã¯èª€ã£ãŠè±èœããŸããããŠãçŽ æŽããããæåŸã®èšå®ãè©ŠããŠã¿ãŸãããã
ãããŠãããã楜ãã¿ãå§ãŸããŸããç§ããããçµã¿ç«ãŠãã®ã¯ãšãŠãéèŠã§ãã
ã¹ã¯ãªãããéžæããŸããããéžæãããŠããŸãããèšå®ã«å ¥ããŸãïŒåã«éžæãããªãã·ã§ã³ããããŸãïŒãç§ã¯éžã¶ãéžã°ããªãããããŠãã-é¡ã®éã«ãããããã«æ°ä»ããŸã§ãåã€æ¹æ³ãèŠã€ãããŸã§ãç§ã¯å€ã殺ããŸããïŒãã¡ã€ã«ãéžæããã ãã§ã¯ã[é©çš]ãã¿ã³ã¯ç°è²ã®ãŸãŸã§ããããšãå€æããŸããããããŠãå€æŽã¯èšæ¶ãããŸãããä»ã®ãã€ã¢ãã°ãã©ã¡ãŒã¿ãç·šéããŠã[é©çš]ãã¿ã³ãé»ãããããšãäžå¯æ¬ ã§ããäžã®åçã§ã¯ãçã£é»ã§ããã°ã¬ãŒè¡šç€ºããããŸãŸã®å Žåãå€æŽã¯ä¿åããããã¹ã¯ãªããã䜿çšããããã«ãã¹ãŠãåæ§æãããããšã¯ãããŸããã
ã¹ã¯ãªããã¯ãŸã äœæäžã§ããããã®ãšã³ãã£ã³ã°ã¯ç§ãã¡ã«ãšã£ãŠãã䟿å©ã«ãªã£ãŠããŸãã
vlog -sv -work UsbHead1 +incdir+C:/Work/UsbHead1/UsbHead1/synthesis/submodules {C:/Work/UsbHead1/UsbHead1/synthesis/submodules/UsbHead1_master_0_timing_adt.sv}
do "C:/Work/UsbHead1/SystemCPlay/myrun.do"
æåŸã«ããããžã§ã¯ãã®ãœãŒã¹ã³ãŒããäœæããããã»ã¹ã¯ãå®å šã«ç§ãã¡ã®è²¬ä»»ã§ããçŽ æŽãããïŒåœæãç§ã¯ã¶ã€ãªã³ã¯ã¹çšã«æžãããModelSimããã¥ã¡ã³ãã䜿çšããSystemCæ€èšŒããèŠã€ããããšãã§ããŸããã§ãããããããModelSimã¯ã¢ããªã«ã®ModelSimã«ãããŸãããã®ããã¥ã¡ã³ãã®äŸãšéå»ã®å®éšã§äœæãããDOãã¡ã€ã«ã®ãµã³ãã«ã䜿çšããŠã次ã®ã¹ã¯ãªããããã¹ããäœæããŸããïŒããŒã®æ°ã«é©ããªãã§ãã ããã以äžã§ã¯ã»ãšãã©ãã¹ãŠãç Žæ£ãã次ã«çµ¶å¯Ÿãã¹ãçžå¯Ÿãã¹ã«çœ®ãæããŸãããã®æ®µéã§ã¯ãäŸãããã¹ãŠãåŒãåºããŸãããããã³èªåçæããããµã³ãã«ïŒã
vlog -vlog01compat -work work +incdir+C:/Work/UsbHead1/SystemCPlay {C:/Work/UsbHead1/SystemCPlay/ulpi_wrapper.v}
vlib sc_work
sccom âg âI C:/intelFPGA_lite/17.1/quartus/cusp/systemc/include âwork sc_work C:/Work/UsbHead1/SystemCPlay/ulpi_driver.cpp
ãã©ã ããŒã«...ãããŠModelSimã¯ç§ãã¡ã«å®£èšããŸãïŒç§ãã¡ã
ãã¹ãŠã®åå£ãªèšèãçç¥ããå Žåãç§ã¯äœãèšãããšã¯ãããŸãã...ãããããã®ãããªéã¯æž¡ãããŸããïŒãããŠãã©ãã§å¥ã®ULPIã¢ãã«ãå ¥æã§ããŸããïŒãã¡ãããFPGAã®æ¬æ Œçãªãããžã§ã¯ãã«å°éçã«æºãã£ãŠããå€åœäººã®å人ã«ãåæããŸãããç¹ã«ç§ã«ãšã£ãŠã圌ãã¯é±æ«ã«ã©ã€ã»ã³ã¹ãããModelSimãåãããã·ã³ãžã®ãªã¢ãŒãã¢ã¯ã»ã¹ãéå§ããŸããã2çªç®ã®ãã³ã±ãŒãããŽããŽãããŠããããšãå€æããŸããã64ãããããŒãžã§ã³ã¯ãã©ã€ã»ã³ã¹ããã圢åŒã§ãã£ãŠããSystemCã§ã¯æ©èœããŸãããããããçµå±ãã©ã€ã»ã³ã¹ãããModelSimã®32ãããããŒãžã§ã³ã§éã¶ããšãã§ããŸããããããã£ãŠãç§ãã¡ã¯ç©èªãç¶ããŸã...
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ãCïŒ\ modeltech_10.2c \ docs \ pdfdocs -PDF圢åŒã®ãã¡ã€ã«ãå«ãããã¥ã¡ã³ããç§ã¯ãã¡ã€ã«modelsim_se_ref.pdfïŒModelSim SEã³ãã³ããªãã¡ã¬ã³ã¹ããã¥ã¢ã«ïŒãmodelsim_se_user.pdfïŒModelSim SEãŠãŒã¶ãŒãºããã¥ã¢ã«ïŒãããã³modelsim_se_tut.pdfïŒModelSim SEãã¥ãŒããªã¢ã«ïŒã奜ãã§ãããèšèªèªäœã«ã€ããŠã¯ããŸããããŸãããããã¡ã€ã«ãæ¥ç¶ããæ¹æ³ãšæ¹èšã®åé¡ã解決ããæ¹æ³ã«ã€ããŠã¯ããªãã§ãã
次ã«ã䟿å©ãªãã£ã¬ã¯ããªCïŒ\ modeltech_10.2c \ examples..ãæ¢è£œã®* .doãã¡ã€ã«ãšæ¢è£œã®cppããã³hãã¡ã€ã«ã®äŸããããŸããç§ãã¡ã«ãšã£ãŠæãæçšãªäŸã¯Cã§ãïŒ\ modeltech_10.2c \ examples \ systemc \ vlog_scãVerilogã³ãŒãããSystemCã³ãŒãã«ã¢ã¯ã»ã¹ããæ¹æ³ã瀺ããŸããæçµçã«ã¯ããŸãã«ãã®ããã«ãªããŸããCïŒ\ modeltech_10.2c \ \ SystemCã®ãã£ã¬ã¯ããªãå«ããã«ã¯ãèšèªã®ã¿ã€ãã©ã€ãã©ãªã®ãœãŒã¹ã³ãŒããå«ãŸããŠããŸããæªããªãã¡ã¬ã³ã¹ããã¯ã§ã¯ãããŸããã圌ããèšãããã«ãéã®ããªãããšãšçã®ããã®éãããŸãã ã«ã¿ãã°ãããã¹ãŠãä»ãããªãã¯èšèªãšãã®äžã®ããã°ã©ãã³ã°æè¡ã®äž¡æ¹ã«ã€ããŠå€ããåŠã¶ããšãã§ããçŽ æŽãããæ¬ã®ã¿ã€ãã«ã§ããSystemC-ãŒãããã第2çãDavid C. BlackãJack DonovanãBill BuntonãAnnaKeistã«ããã
SystemCãã€ã¢ã¬ã¯ã
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ãm_vpi_handle= vpi_handle_by_nameïŒïŒconst char *ïŒnameãNULLïŒ;
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// Update systemC TB
if(sc_pending_activity())
sc_start((int)(time_value-m_last_time),SC_NS);
æªãèããæãèµ·ãããããã©ã€ãã©ãªã«ã¯sc_pending_activityïŒïŒé¢æ°ã¯ãããŸãããsc_pending_activity_at_current_timeïŒïŒé¢æ°ããããŸãããç§ã¯ãããåŠçããããšããããŸããã§ãããåã®èª¬æã®ä»£ããã«ãç§ã¯ãã³ããäžã
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ããªãã¯ãã¹ãŠãæžãçŽãããšããããšãã§ããŸã...ããããããã¯å¿ èŠã§ããïŒæºåãã§ããŠãããã®ããã¹ãŠäœ¿ãããã£ãã®ã§ãå®éã«ããããã¹ãŠå§ããããšãæãåºãããŠãã ãããæ¬åœã«å€ãã®æéãç¡é§ã«ããã°ãçŽç²ãªSystemVerilogã§ç¡æã®ç°å¢ã§ãã¹ãŠãéçºã§ããŸã...æéãç¡é§ã«ããã®ã§ã¯ãªããç¯çŽããããã«ããã«è¡ããŸããïŒãããå®éã«ã¯...äž»ãªããšã¯ç§ãã¡ãããŠããããšãå¿ããªãããšã§ããULPIãã¹ã¢ãã«ã䜿çšããããšæããŸãã圌女ã¯éãŸã£ããäŸããå®å šãªãã¹ãã·ã¹ãã ãæ§ç¯ããããšãããšåé¡ãçºçããŸãã...ããã¯ãªãã§ããïŒãŸããå®å šãªã·ã¹ãã ã¯æ©èœããŸããããããŠå€§äžå€«ã§ããã·ã¹ãã ã®åäœãèŠãã«ãè©Šè¡é¯èª€ããªãã1ã€ã®ã¢ãã«ããã¹ã¿ãŒããŸãã
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ModelSimã®é ä¿¡ããã®ãµã³ãã«* .doãã¡ã€ã«ã調ã¹ãŠãã¹ã¯ãªãããå€§å¹ ã«ç°¡ç¥åããæçµçã«æ¬¡ã®ããã«ããŸããã
vlog +../../SystemCPlay {../../MyCores/ULPIhead.sv}
sccom -g ../../SystemCPlay/ulpi_driver.cpp
sccom -link
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SC_MODULE_EXPORT(ulpi_driver);
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ã¢ãã«ã«ã¯å®éã®ULPIãšã¯ããã€ãã®éããããããšãå€æããŸãããæåã®éãã¯ã66MHzã®ã¯ããã¯ããããã§çæããå¿ èŠãããããšã§ããã¢ãã«ã«ã¯äœã衚瀺ãããŸããïŒ
sc_in<bool> clk_i;
é害ïŒãªã¯ãŒã¯ãå§ããŸãããïŒç¹ã«æèšãããŠããªãéãããã¹ãŠã®äœæ¥ã¯ulpi_driver.hãã¡ã€ã«ã§å®è¡ãããŸãã
ããŒãã¿ã€ããå€æŽããŸããããã ã£ãïŒ
sc_in<bool> clk_i;
ã«ãªããŸããïŒããŒãåãå€æŽããŸããïŒïŒ
sc_inout<bool> clk;
ç§ã¯æ¬ãããå€æ°ãè¿œå ããããšã«ãã£ãŠå®éã®ãžã§ãã¬ãŒã¿ãŒãæ¿å ¥ãããããšãåŠã³ãŸããã
sc_clock oscillator;
ã³ã³ã¹ãã©ã¯ã¿ãŒã§ãã©ã¡ãŒã¿ãŒãèšå®ããŸãããã®çµæãã³ã³ã¹ãã©ã¯ã¿ãŒã¯æ¬¡ã®åœ¢åŒã«ãªããŸãã
//-------------------------------------------------------------
// Constructor
//-------------------------------------------------------------
SC_HAS_PROCESS(ulpi_driver);
ulpi_driver(sc_module_name name): sc_module(name),
m_tx_fifo(1024),
m_rx_fifo(1024),
oscillator ("clk66",sc_time(15,SC_NS))
{
æåŸã®è¡ã¯ããã ãã§ããå¿ èŠã«å¿ããŠãã·ãã¥ã¬ãŒã·ã§ã³ãéå§ããusb_driverã¢ãžã¥ãŒã«ãããã«ã¯ãªãã¯ããŠãããclk66ãäžæçãªå°å±ã«åŒã£åŒµã£ãŠãã·ãã¥ã¬ãŒã·ã§ã³ããã»ã¹ãå°ãå®è¡ããããšãã§ããŸãããžã§ãã¬ãŒã¿ãã©ã®ããã«æ©èœãããã¯ãã§ã«èŠãŠããŸãã
ãã¡ã€ã³ã¹ã¬ãããéå§ããå Žæã§ã¯ããã¯ä¿¡å·ã®ååãå€æŽããããšãå¿ããªãã§ãã ãããããã ã£ãïŒ
SC_CTHREAD(drive, clk_i.pos());
ãªããŸããïŒ
SC_CTHREAD(drive, clk.pos());
å éšãªã³ã¯ã¯çœ®ãæããããŸãããããããä¿¡å·ãå€ã«åºãããšãã©ãã»ã©çŸããããç§ã¯èŠã€ããŸããã§ãããããããç§ã¯è³æ Œãäžè¶³ããŠããŸããããããã©ãããããããããŒããåŒãåºããã¹ãŠã®è©Šã¿ã¯å€±æããŸããããã€ãäœããéªéã§ããããããã©ãŒã©ã ã§ãèè ãåãããšãããå¿ èŠããããã£ã¹ã«ãã·ã§ã³ãèŠã€ããŸãããããŒã ã¯ãå ¥åããŒãã«ã®ã¿è»¢éã§ãããšå€æããŸãããããããç§ãã¡ã¯åºãŠè¡ãå¿ èŠããããŸãïŒãããã£ãŠããããè¡ããŸãã
ã³ã³ã¹ãã©ã¯ã¿ãŒã®äžã«ã¹ããªãŒã é¢æ°ãè¿œå ããŸãã
void clkThread(void)
{
while (true)
{
wait(oscillator.posedge_event());
clk.write (true);
wait(oscillator.negedge_event());
clk.write (false);
}
}
ãããŠãã¯ã©ã¹ã³ã³ã¹ãã©ã¯ã¿ãŒã«ãªã³ã¯ãè¿œå ããŸãã
SC_THREAD(clkThread);
çŸåšã®çµæã®å šäœåã瀺ãããã«ãçŸåšã®ã³ã³ã¹ãã©ã¯ã¿ãŒé åã瀺ããŸãã
SC_HAS_PROCESS(ulpi_driver);
ulpi_driver(sc_module_name name): sc_module(name),
m_tx_fifo(1024),
m_rx_fifo(1024),
oscillator ("clk66",sc_time(15,SC_NS))
{
SC_CTHREAD(drive,clk.pos());
SC_THREAD(clkThread);
m_reg[ULPI_REG_VIDL] = 0x24;
m_reg[ULPI_REG_VIDH] = 0x04;
m_reg[ULPI_REG_PIDL] = 0x04;
m_reg[ULPI_REG_PIDH] = 0x00;
m_reg[ULPI_REG_FUNC] = 0x41;
m_reg[ULPI_REG_OTG] = 0x06;
m_reg[ULPI_REG_SCRATCH] = 0x00;
}
void clkThread(void)
{
while (true)
{
wait(oscillator.posedge_event());
clk.write (true);
wait(oscillator.negedge_event());
clk.write (false);
}
}
ãã¹ãŠãæåã®ç·šéãå®äºããŸããã
åæ¹åããŒã¿ãã¹ã®äœæ
ULPIã«ã¯åæ¹åããŒã¿ãã¹ããããŸãããããŠãã¢ãã«ã«ã¯æ¬¡ã®èª¬æããããŸãã
sc_out <sc_uint<8> > ulpi_data_o;
sc_in <sc_uint<8> > ulpi_data_i;
é害ïŒæåã«åºåãã¹ã«åºã¥ããŠãã©ã³ã¯ãäœæãã次ã«ãã¹ãŠãããã«åãæ¿ããŸããã©ãããå§ããŸããïŒãã¹ã¯3çªç®ã®ç¶æ ã«å ¥ãããšãã§ããªããã°ãªãããsc_uint <8>ã¿ã€ãã¯ãã€ããªããŒã¿ã§ã®ã¿æ©èœãããšããäºå®ãããsc_lv <8>ã¿ã€ãã圹ã«ç«ã¡ãŸãããããã£ãŠãã¿ã€ã€å®£èšã次ã®ããã«å€æŽããŸãã
sc_inout <sc_lv<8> > ulpi_data_o;
次ã«ãulpi_driver.cppãã¡ã€ã«ã«ç§»åããããã§ulpi_data_oãã¹ãžã®ãã¹ãŠã®åŒã³åºããæ¢ããŸããçŽæçã«ãä¿®æ£ããå Žæã¯1ã€ãããªãããšã«æ°ä»ããŸããã
åãããã¹ãã
void ulpi_driver::drive_input(void)
{
// Turnaround
ulpi_dir_o.write(false);
ulpi_nxt_o.write(false);
ulpi_data_o.write(0x00);
wait(oscillator.posedge_event());
}
éžæããè¡ãã«å€æŽããŸã
ulpi_data_o.write("ZZZZZZZZ");
ãã¹ãŠãããã§ã2è¡ã®ä»£ããã«æ¬¡ã®ããšãã§ããŸãã
sc_inout <sc_lv<8> > ulpi_data_o;
sc_in <sc_uint<8> > ulpi_data_i;
1ã€æžãïŒ
sc_inout <sc_lv<8> > ulpi_data;
ãããŠãh-nickãšcpp-shnikã®äž¡æ¹ã®å€ãå€æ°ãžã®ãã¹ãŠã®åç §ãulpi_dataå€æ°ãžã®åç §ã«çœ®ãæããŸãã
ããŒããšã€ãªã¢ã¹ãè¿œå ãã
ãããé·ãæ€çŽ¢ã®çµæãModelSimç°å¢ã§ã¯ãGUIã䜿çšããŠSystemCã®å¥ã®ã¢ãžã¥ãŒã«ã®ããŒããç°¡åã«ååŸããŠç¢ºèªã§ãããšããçµè«ã«éããŸããïŒãããã誀ãã§ãïŒããã ãããã®ã¢ãžã¥ãŒã«ããã¹ãã·ã¹ãã ã«æ¿å ¥ãããšã衚瀺ãããŸããããããçè«ã調ã¹ãŠãããã¡ã«ãããŒãåã®ãšã€ãªã¢ã¹ãçŸããèšå®ããæ¹æ³ãèŠã€ããŸãããæçµçãªã¯ã©ã¹ã³ã³ã¹ãã©ã¯ã¿ã¯æ¬¡ã®ããã«ãªããŸãã
SC_HAS_PROCESS(ulpi_driver);
ulpi_driver(sc_module_name name): sc_module(name),
m_tx_fifo(1024),
m_rx_fifo(1024),
oscillator ("clk66",sc_time(15,SC_NS)),
rst_i ("rst"),
ulpi_data ("data"),
ulpi_dir_o ("dir"),
ulpi_nxt_o ("nxt"),
ulpi_stp_i ("stp")
{
SC_CTHREAD(drive,clk.pos());
SC_THREAD(clkThread);
m_reg[ULPI_REG_VIDL] = 0x24;
m_reg[ULPI_REG_VIDH] = 0x04;
m_reg[ULPI_REG_PIDL] = 0x04;
m_reg[ULPI_REG_PIDH] = 0x00;
m_reg[ULPI_REG_FUNC] = 0x41;
m_reg[ULPI_REG_OTG] = 0x06;
m_reg[ULPI_REG_SCRATCH] = 0x00;
}
ãã¹ãã·ã¹ãã ã®äœæ
ãããã 2ã€ã®ãããã°ãããã¢ãžã¥ãŒã«ïŒã¢ãã©ã€ã¶ãŒããããšULPIãã¹ã¢ãã«ïŒããã¹ããã¡ã€ã«èªäœã«ãžã£ã³ãããããã«ããã¹ãŠãèªåçã«å®è¡ããããšã«æåããŸããã§ãããããããå°ãªããšãããããã¹ããè¡ããããã«ULPIãè¿œå ããŸããããååã®èšäºã®ææ³ã䜿çšããŠãULPIhead.svãã¡ã€ã«ã®ãã¹ãã·ã¹ãã ãäœæããŸãããsim1.vãšãããã¡ã€ã«ããããããã«sim1.svãšããååã«å€æŽããŸããã
次ã«ããã³ãã«ä»ãã®ulpi_driverã¢ãžã¥ãŒã«ãè¿œå ããŸãããçµæã®ã¹ã¯ãªããmyrun.doã¯æ¬¡ã®ããã«ãªããŸãã
vlog +../../SystemCPlay {../../MyCores/ULPIhead.sv}
sccom -g ../../SystemCPlay/ulpi_driver.cpp
sccom -link
vlog +../../SystemCPlay {../../SystemCPlay/sim1.sv}
vsim -voptargs="+acc" sim1
æåŸã®è¡ã¯æ·åãããŠããŸããããããªããã°ãVerilogã³ãŒãã«ã¯ããŒãããããŸããã§ãããæé©åãã©ã¡ãŒã¿ãå€æŽããããšã§ããã®åé¡ã解æ¶ããŸããç§ã¯ãããããã¹ãŠããŸã ãã·ã³äžã§è¡ãããŠããæåã®æ®µéã§ã·ã¹ãã ãã·ãã¥ã¬ãŒãããããã«äœæããã* .doãã¡ã€ã«ã§èŠãŸããã確ãã«ãé·ãåããããŸããåé¡ã解決ããéµãèŠã€ããŠã³ããŒããŸãããã ãã-ç§ã¯é·ãåã奜ãã§ã¯ãããŸãããç§ã¯äžèŠãªãã®ããã¹ãŠæšãŠãŸããã
次ã«ãULPIãããã¯ããã¹ãã·ã¹ãã ã«è¿œå ãããããŒãã¹ããäœæããŸãããã¹ãŠã®ã¯ããã¯ä¿¡å·ãã«ãã«ãé³ãããŠãŠããããã¹ãæ£ããå€ã«èšå®ãããŠããããšã確èªããããã§ãã
ç§ã¯ãã®ãã¹ããåããŸããã
ããã¹ããèŠãŠãã ããã
`timescale 1ns / 1ns
module sim1 ;
reg ulpi_dir ;
wire source_valid ;
wire ulpi_stp ;
reg ulpi_clk ;
reg ulpi_nxt ;
reg reset_n ;
reg read ;
reg [31:0] writedata ;
wire ulpi_rst ;
reg clk ;
wire [7:0] source_data ;
reg write ;
wire [7:0] ulpi_data ;
reg source_ready ;
reg [1:0] address ;
wire [31:0] readdata ;
always
begin
clk = 1;
#5;
clk = 0;
#5;
end
ULPIhead DUT
(
.ulpi_dir (ulpi_dir ) ,
.source_valid (source_valid ) ,
.ulpi_stp (ulpi_stp ) ,
.ulpi_clk (ulpi_clk ) ,
.ulpi_nxt (ulpi_nxt ) ,
.reset_n (reset_n ) ,
.read (read ) ,
.writedata (writedata ) ,
.ulpi_rst (ulpi_rst ) ,
.clk (clk ) ,
.source_data (source_data ) ,
.write (write ) ,
.ulpi_data (ulpi_data ) ,
.source_ready (source_ready ) ,
.address (address ) ,
.readdata (readdata ) );
ulpi_driver ULPI
(
.clk (ulpi_clk),
.rst (ulpi_rst),
.data (ulpi_data),
.dir (ulpi_dir),
.nxt (ulpi_nxt),
.stp (ulpi_stp)
);
initial
begin
reset_n = 1'b0;
source_ready = 1;
writedata = 0;
address = 0;
read = 0;
write = 0;
#20
reset_n = 1'b1;
end
endmodule
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